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89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash preliminary specification supersedes data of 1997 dec 02 ic20 data handbook 1998 apr 24 integrated circuits
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 2 1998 apr 24 description the 89C536/89c538 are single-chip 8-bit microcontrollers manufactured in advanced cmos process and are derivatives of the 80c51 microcontroller family. all the devices have the same instruction set as the 80c51. the devices also have four 8-bit i/o ports, three 16-bit timer/event counters, a multi-source, two-priority-level, nested interrupt structure, uart and on-chip oscillator and timing circuits. for systems that require extra data memory capability up to 64k bytes, each can be expanded using standard ttl-compatible memories and logic. the 89C536/89c538 contain a non-volatile flash program memory (16k bytes in the 89C536, and 64k bytes in the 89c538). the devices have 512 bytes of ram data memory. features ? 80c51 central processing unit ? 16k 8 (89C536) or 64k 8 (89c538), flash eprom program memory ? 512 8 ram, externally expandable to 64k 8 data memory ? three 16-bit counter/timers ? up to 3 external interrupt request inputs ? 6 interrupt sources with 2 priority levels ? four 8-bit i/o ports ? full-duplex uart ? power control modes idle mode power down mode, with wakeup from power down using external interrupt ? 44-pin plcc and qfp packages ordering information part number memory size temperature range ( c) and package freq. (mhz) drawing number p89C536nba a 16k bytes 0 to +70, 44-pin plastic leaded chip carrier 33 sot187-2 p89C536nbb b 16k bytes 0 to +70, 44-pin plastic quad flat package 33 sot307-2 p89c538nba a 64k bytes 0 to +70, 44-pin plastic leaded chip carrier 33 sot187-2 p89c538nbb b 64k bytes 0 to +70, 44-pin plastic quad flat package 33 sot307-2
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 3 block diagram pointer timing control psen ea v pp ale/prog rst xtal1 xtal2 v cc v ss port 0 drivers port 2 drivers ram addr register ram port 0 latch port 2 latch rof/ eprom register b acc stack tmp2 tmp1 alu and instruction register pd oscillator psw port 1 latch port 3 latch port 1 drivers port 3 drivers program address register buffer pc incre- menter program counter dptr's multiple p1.0p1.7 p3.0p3.7 p0.0p0.7 p2.0p2.7 sfrs timers su00854 8 8 16 logic symbol port 0 port 1 port 2 port 3 address and data bus address bus t2 t2ex rxd txd int0 int1 t0 t1 wr rd secondary functions rst ea /v pp psen ale/prog v ss v cc xtal1 xtal2 su00830 programming information: programmers are provided by: company phone number internet address advin 18006272456 bp microsystem 18002252102 http://www.bpmicro.com data i/o 12068816444 http://www.dataio.com hilo
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 4 plastic leaded chip carrier pin functions lcc 6140 7 17 39 29 18 28 pin function 1 nic* 2 p1.0/t2 3 p1.1/t2ex 4 p1.2/eci 5 p1.3/cex0 6 p1.4/cex1 7 p1.5/cex2 8 p1.6/cex3 9 p1.7/cex4 10 rst 11 p3.0/rxd 12 nic* 13 p3.1/txd 14 p3.2/int0 15 p3.3/int1 pin function 16 p3.4/t0 17 p3.5/t1 18 p3.6/wr 19 p3.7/rd 20 xtal2 21 xtal1 22 v ss 23 nic* 24 p2.0/a8 25 p2.1/a9 26 p2.2/a10 27 p2.3/a11 28 p2.4/a12 29 p2.5/a13 30 p2.6/a14 pin function 31 p2.7/a15 32 psen 33 ale/prog 34 nic* 35 ea /v pp 36 p0.7/ad7 37 p0.6/ad6 38 p0.5/ad5 39 p0.4/ad4 40 p0.3/ad3 41 p0.2/ad2 42 p0.1/ad1 43 p0.0/ad0 44 v cc su00023 * no internal connection plastic quad flat pack pin functions pqfp 44 34 1 11 33 23 12 22 pin function 1 p1.5/cex2 2 p1.6/cex3 3 p1.7/cex4 4 rst 5 p3.0/rxd 6 nic* 7 p3.1/txd 8 p3.2/int0 9 p3.3/int1 10 p3.4/t0 11 p3.5/t1 12 p3.6/wr 13 p3.7/rd 14 xtal2 15 xtal1 pin function 16 v ss 17 nic* 18 p2.0/a8 19 p2.1/a9 20 p2.2/a10 21 p2.3/a11 22 p2.4/a12 23 p2.5/a13 24 p2.6/a14 25 p2.7/a15 26 psen 27 ale/prog 28 nic* 29 ea /v pp 30 p0.7/ad7 pin function 31 p0.6/ad6 32 p0.5/ad5 33 p0.4/ad4 34 p0.3/ad3 35 p0.2/ad2 36 p0.1/ad1 37 p0.0/ad0 38 v cc 39 nic* 40 p1.0/t2 41 p1.1/t2ex 42 p1.2/eci 43 p1.3/cex0 44 p1.4/cex1 su00024 * no internal connection
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 5 pin descriptions pin number mnemonic lcc qfp type name and function v ss 1, 22 16, 39 i ground: 0v reference. v cc 23, 44 17, 38 i power supply: this is the power supply voltage for normal, idle, and power-down operation. p0.00.7 4336 3730 i/o port 0: port 0 is an open-drain, bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application, it uses strong internal pull-ups when emitting 1s. port 0 also outputs the code bytes during program verification and received code bytes during eeprom programming. external pull-ups are required during program verification. p1.0p1.7 29 4044, 13 i/o port 1: port 1 is an 8-bit bidirectional i/o port with internal pull-ups. port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: i il ). port 1 also receives the low-order address byte during program memory verification. alternate functions for port 1 include: 2 40 i/o t2 (p1.0): timer/counter 2 external count input 3 41 i t2ex (p1.1): timer/counter 2 reload/capture p2.0p2.7 2431 1825 i/o port 2: port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: i il ). port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application, it uses strong internal pull-ups when em itting 1s. some port 2 pins receive the high order address bits during eeprom programming and verification. p3.0p3.7 11, 1319 5, 713 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (see dc electrical characteristics: i il ). port 3 also serves the special features of the 80c51 family, as listed below: 11 5 i rxd (p3.0): serial input port 13 7 o txd (p3.1): serial output port 14 8 i int0 (p3.2): external interrupt 15 9 i int1 (p3.3): external interrupt 16 10 i t0 (p3.4): timer 0 external input 17 11 i t1 (p3.5): timer 1 external input 18 12 o wr (p3.6): external data memory write strobe 19 13 o rd (p3.7): external data memory read strobe rst 10 4 i reset: a high on this pin for two machine cycles while the oscillator is running, resets the device. an internal diffused resistor to v ss permits a power-on reset using only an external capacitor to v cc . ale/prog 33 27 o address latch enable/program pulse: output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. this pin is also the program pulse input (prog ) during eeprom programming. psen 32 26 o program store enable: the read strobe to external program memory. when the processor is executing code from the external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. ea /v pp 35 29 i external access enable/programming supply voltage: ea must be externally held low to enable the device to fetch code from external program memory. if ea is held high, the device executes from internal program memory. this pin also receives the 12v programming supply voltage (v pp ) during eprom programming. ea is internally latched on reset. xtal1 21 15 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal2 20 14 o crystal 2: output from the inverting oscillator amplifier. note: to avoid alatch-upo effect at power-on, the voltage on any pin at any time must not be higher than v cc + 0.5v or v ss 0.5v, respectively.
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 6 table 1. special function registers symbol description direct address bit address, symbol, or alternative port function msb lsb reset value acc* accumulator e0h e7 e6 e5 e4 e3 e2 e1 e0 00h b* b register f0h f7 f6 f5 f4 f3 f2 f1 f0 00h dptr: data pointer (2 bytes) dph data pointer high 83h 00h dpl data pointer low 82h 00h af ae ad ac ab aa a9 a8 ie* interrupt enable a8h ea et2 es et1 ex1 et0 ex0 00h bf be bd bc bb ba b9 b8 ip* interrupt priority b8h pt2 ps pt1 px1 pt0 px0 x0000000b 87 86 85 84 83 82 81 80 p0* port 0 80h ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ffh 97 96 95 94 93 92 91 90 p1* port 1 90h t2ex t2 ffh a7 a6 a5 a4 a3 a2 a1 a0 p2* port 2 a0h ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ffh b7 b6 b5 b4 b3 b2 b1 b0 p3* port 3 b0h rd wr t1 t0 int1 int0 txd rxd ffh pcon# power control 87h smod extram gf1 gf0 pd idl 00xx0000b d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov p 00h racap2h # timer 2 capture high cbh 00h racap2l # timer 2 capture low cah 00h sbuf serial data buffer 99h xxxxxxxxb 9f 9e 9d 9c 9b 9a 99 98 scon* serial control 98h sm0 sm1 sm2 ren tb8 rb8 ti ri 00h sp stack pointer 81h 07h 8f 8e 8d 8c 8b 8a 89 88 tcon* timer control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h cf ce cd cc cb ca c9 c8 t2con* timer 2 control c8h tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 00h th0 timer high 0 8ch 00h th1 timer high 1 8dh 00h th2# timer high 2 cdh 00h tl0 timer low 0 8ah 00h tl1 timer low 1 8bh 00h tl2# timer low 2 cch 00h tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 00h * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs. reserved bits.
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 7 oscillator characteristics xtal1 and xtal2 are the input and output, respectively, of an inverting amplifier. the pins can be configured for use as an on-chip oscillator. to drive the device from an external clock source, xtal1 should be driven while xtal2 is left unconnected. there are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. however, minimum and maximum high and low times specified in the data sheet must be observed. reset a reset is accomplished by holding the rst pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. to insure a good power-on reset, the rst pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. at power-on, the voltage on v cc and rst must come up at the same time for a proper start-up. ports 1, 2, and 3 will asynchronously be driven to their reset condition when a voltage above v ih1 (min.) is applied to reset. low power modes idle mode in the idle mode (see table 2), the cpu puts itself to sleep while all of the on-chip peripherals stay active. the instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. the cpu contents, the on-chip ram, and all of the special function registers remain intact during this mode. the idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. power-down mode to save even more power, a power down mode (see table 2) can be invoked by software. in this mode, the oscillator is stopped and the instruction that invoked power down is the last instruction executed. the on-chip ram and special function registers retain their values down to 2.0v and care must be taken to return v cc to the minimum specified operating voltages before the power down mode is terminated. either a hardware reset or external interrupt can be used to exit from power down. reset redefines all the sfrs but does not change the on-chip ram. an external interrupt allows both the sfrs and the on-chip ram to retain their values. to properly terminate power down the reset or external interrupt should not be executed before v cc is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10ms). with an external interrupt, int0 and int1 must be enabled and configured as level-sensitive. holding the pin low restarts the oscillator but bringing the pin back high completes the exit. once the interrupt is serviced, the next instruction to be executed after reti will be the one following the instruction that put the device into power down. design consideration ? to eliminate the possibility of an unexpected write when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to memory. table 2. external pin status during idle and power-down mode mode program memory ale psen port 0 port 1 port 2 port 3 idle internal 1 1 data data data data idle external 1 1 float data address data power-down internal 0 0 data data data data power-down external 0 0 float data data data
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 8 timer 2 operation timer 2 timer 2 is a 16-bit timer/counter which can operate as either an event timer or an event counter, as selected by c/t2* in the special function register t2con (see figure 1). timer 2 has three operating modes:capture, auto-reload, and baud rate generator, which are selected by bits in the t2con as shown in table 3. capture mode in the capture mode there are two options which are selected by bit exen2 in t2con. if exen2=0, then timer 2 is a 16-bit timer or counter (as selected by c/t2* in t2con) which, upon overflowing sets bit tf2, the timer 2 overflow bit. this bit can be used to generate an interrupt (by enabling the timer 2 interrupt bit in the ie register/sfr table). if exen2= 1, timer 2 operates as described above, but with the added feature that a 1- to -0 transition at external input t2ex causes the current value in the timer 2 registers, tl2 and th2, to be captured into registers rcap2l and rcap2h, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set, and exf2 like tf2 can generate an interrupt (which vectors to the same location as timer 2 overflow interrupt. the timer 2 interrupt service routine can interrogate tf2 and exf2 to determine which event caused the interrupt). the capture mode is illustrated in figure 2 (there is no reload value for tl2 and th2 in this mode. even when a capture event occurs from t2ex, the counter keeps on counting t2ex pin transitions or osc/12 pulses.). auto-reload mode in the 16-bit auto-reload mode, timer 2 can be configured as either a timer or counter (c/t2* in t2con). figure 3 shows the autoreload mode of timer 2. in this mode there are two options selected by bit exen2 in t2con register. if exen2=0, then timer 2 counts up to 0ffffh and sets the tf2 (overflow flag) bit upon overflow. this causes the timer 2 registers to be reloaded with the 16-bit value in rcap2l and rcap2h. the values in rcap2l and rcap2h are preset by software. if exen2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input t2ex. this transition also sets the exf2 bit. the timer 2 interrupt, if enabled, can be generated when either tf2 or exf2 are 1. the external flag exf2 toggles when timer 2 underflows or overflows. this exf2 bit can be used as a 17th bit of resolution if needed. the exf2 flag does not generate an interrupt in this mode of operation. (msb) (lsb) symbol position name and significance tf2 t2con.7 timer 2 overflow flag set by a timer 2 overflow and must be cleared by software. tf2 will not be set when either rclk or tclk = 1. exf2 t2con.6 timer 2 external flag set when either a capture or reload is caused by a negative transition on t2ex and exen2 = 1. when timer 2 interrupt is enabled, exf2 = 1 will cause the cpu to vector to the timer 2 interrupt routine. exf2 must be cleared by software. rclk t2con.5 receive clock flag. when set, causes the serial port to use timer 2 overflow pulses for its receive clock in modes 1 and 3. rclk = 0 causes timer 1 overflow to be used for the receive clock. tclk t2con.4 transmit clock flag. when set, causes the serial port to use timer 2 overflow pulses for its transmit clock in modes 1 and 3. tclk = 0 causes timer 1 overflows to be used for the transmit clock. exen2 t2con.3 timer 2 external enable flag. when set, allows a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. exen2 = 0 causes timer 2 to ignore events at t2ex. tr2 t2con.2 start/stop control for timer 2. a logic 1 starts the timer. c/t2 t2con.1 timer or counter select. (timer 2) 0 = internal timer (osc/12) 1 = external event counter (falling edge triggered). cp/rl2 t2con.0 capture/reload flag. when set, captures will occur on negative transitions at t2ex if exen2 = 1. when cleared, auto-reloads will occur either with timer 2 overflows or negative transitions at t2ex when exen2 = 1. when either rclk = 1 or tclk = 1, this bit is ignored and the timer is forced to auto-reload on timer 2 overflow. tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 su00866 figure 1. timer/counter 2 (t2con) control register table 3. timer 2 operating modes rclk + tclk cp/rl2 tr2 mode 0 0 1 16-bit auto-reload 0 1 1 16-bit capture 1 x 1 baud rate generator x x 0 (off)
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 9 osc 12 c/t2 = 0 c/t2 = 1 tr2 control tl2 (8-bits) th2 (8-bits) tf2 rcap2l rcap2h exen2 control exf2 timer 2 interrupt t2ex pin transition detector t2 pin capture su00066 figure 2. timer 2 in capture mode osc 12 c/t2 = 0 c/t2 = 1 tr2 control tl2 (8-bits) th2 (8-bits) tf2 rcap2l rcap2h exen2 control exf2 timer 2 interrupt t2ex pin transition detector t2 pin reload su00067 figure 3. timer 2 in auto-reload mode
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 10 osc 2 c/t2 = 0 c/t2 = 1 tr2 control tl2 (8-bits) th2 (8-bits) 16 rcap2l rcap2h exen2 control exf2 timer 2 interrupt t2ex pin transition detector t2 pin reload note: osc. freq. is divided by 2, not 12. 2 a0o a1o rx clock 16 tx clock a0o a1o a0o a1o timer 1 overflow note availability of additional external interrupt. smod rclk tclk su00068 figure 4. timer 2 in baud rate generator mode table 4. timer 2 generated commonly used baud rates ba d rate osc freq timer 2 ba u d rate osc freq rcap2h rcap2l 375k 12mhz ff ff 9.6k 12mhz ff d9 2.8k 12mhz ff b2 2.4k 12mhz ff 64 1.2k 12mhz fe c8 300 12mhz fb 1e 110 12mhz f2 af 300 6mhz fd 8f 110 6mhz f9 57 baud rate generator mode bits tclk and/or rclk in t2con (table 3) allow the serial port transmit and receive baud rates to be derived from either timer 1 or timer 2. when tclk= 0, timer 1 is used as the serial port transmit baud rate generator. when tclk= 1, timer 2 is used as the serial port transmit baud rate generator. rclk has the same effect for the serial port receive baud rate. with these two bits, the serial port can have different receive and transmit baud rates one generated by timer 1, the other by timer 2. figure 4 shows the timer 2 in baud rate generation mode. the baud rate generation mode is like the auto-reload mode,in that a rollover in th2 causes the timer 2 registers to be reloaded with the 16-bit value in registers rcap2h and rcap2l, which are preset by software. the baud rates in modes 1 and 3 are determined by timer 2's overflow rate given below: modes 1 and 3 baud rates timer 2 overflow rate 16 the timer can be configured for either atimero or acountero operation. in many applications, it is configured for atimero operation (c/t2*=0). timer operation is different for timer 2 when it is being used as a baud rate generator. usually, as a timer it would increment every machine cycle (i.e., 1/12 the oscillator frequency). as a baud rate generator, it increments every state time (i.e., 1/2 the oscillator frequency). thus the baud rate formula is as follows: oscillator frequency [32 [65536 (rcap2h, rcap2l)]] modes 1 and 3 baud rates = where: (rcap2h, rcap2l)= the content of rcap2h and rcap2l taken as a 16-bit unsigned integer. the timer 2 as a baud rate generator mode shown in figure 4, is valid only if rclk and/or tclk = 1 in t2con register. note that a rollover in th2 does not set tf2, and will not generate an interrupt. thus, the timer 2 interrupt does not have to be disabled when timer 2 is in the baud rate generator mode. also if the exen2 (t2 external enable flag) is set, a 1-to-0 transition in t2ex (timer/counter 2 trigger input) will set exf2 (t2 external flag) but will not cause a reload from (rcap2h, rcap2l) to (th2,tl2). therefore when timer 2 is in use as a baud rate generator, t2ex can be used as an additional external interrupt, if needed.
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 11 when timer 2 is in the baud rate generator mode, one should not try to read or write th2 and tl2. as a baud rate generator, timer 2 is incremented every state time (osc/2) or asynchronously from pin t2; under these conditions, a read or write of th2 or tl2 may not be accurate. the rcap2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. the timer should be turned off (clear tr2) before accessing the timer 2 or rcap2 registers. table 4 shows commonly used baud rates and how they can be obtained from timer 2. summary of baud rate equations timer 2 is in baud rate generating mode. if timer 2 is being clocked through pin t2(p1.0) the baud rate is: baud rate timer 2 overflow rate 16 if timer 2 is being clocked internally , the baud rate is: baud rate f osc [32 [65536 (rcap2h, rcap2l)]] where f osc = oscillator frequency to obtain the reload value for rcap2h and rcap2l, the above equation can be rewritten as: rcap2h, rcap2l 65536 f osc 32 baud rate timer/counter 2 set-up except for the baud rate generator mode, the values given for t2con do not include the setting of the tr2 bit. therefore, bit tr2 must be set, separately, to turn the timer on. see table 5 for set-up of timer 2 as a timer. also see table 6 for set-up of timer 2 as a counter. table 5. timer 2 as a timer t2con mode internal control (note 1) external control (note 2) 16-bit auto-reload 00h 08h 16-bit capture 01h 09h baud rate generator receive and transmit same baud rate 34h 36h receive only 24h 26h transmit only 14h 16h table 6. timer 2 as a counter tmod mode internal control (note 1) external control (note 2) 16-bit 02h 0ah auto-reload 03h 0bh notes: 1. capture/reload occurs only on timer/counter overflow. 2. capture/reload occurs on timer/counter overflow and a 1-to-0 transition on t2ex (p1.1) pin except when timer 2 is used in the baud rate generator mode.
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 12 serial interface the 89c538/536 has a standard 80c51 serial port. this serial port can operate in 4 modes: mode 0: serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted/received (lsb first). the baud rate is fixed at 1/12 the oscillator frequency. mode 1: 10 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in special function register scon. the baud rate is variable. mode 2: 11 bits are transmitted (through txd) or received (through rxd): start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8 in scon) can be assigned the value of 0 or 1, or, for example, the parity bit (p, in the psw) could be moved into tb8. on receive, the 9th data bit goes into rb8 in special function register scon, while the stop bit is ignored. the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. mode 3: 11 bits are transmitted (through txd) or received (through jrxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable. in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren = 1. serial port control register the serial port control and status register is the special function register scon, shown in figure 5. this register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (tb8 and rb8), and the serial port interrupt bits (ti and ri). additional details of serial port operation may be found in the 80c51 family hardware description found in the philips 80c51based 8bit microcontroller data handbook, ic20 . scon address = 98h reset value = 0000 0000b sm0 sm1 sm2 ren tb8 rb8 tl rl bit addressable symbol function sm0 serial port mode bit 0 sm1 serial port mode bit 1 sm0 sm1 mode description baud rate** 0 0 0 shift register f osc /12 0 1 1 8-bit uart variable 1 0 2 9-bit uart f osc /64 or f osc /32 1 1 3 9-bit uart variable sm2 enables the automatic address recognition feature in modes 2 or 3. if sm2 = 1 then rl will not be set unless the received 9th data bit (rb8) is 1, indicating an address, and the received byte is a given or broadcast address. in mode 1, if sm2 = 1 then rl will not be activated unless a valid stop bit was received, and the received byte is a given or broadcast address. in mode 0, sm2 should be 0. ren enables serial reception. set by software to enable reception. clear by software to disable reception. tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. rb8 in modes 2 and 3, the 9th data bit that was received. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. tl transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. must be cleared by software. rl receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see sm2). must be cleared by software. note: **f osc = oscillator frequency su00867 bit: 76543210 figure 5. scon: serial port control register
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 13 interrupt priority structure the 89C536/538 has a 6-source two-level interrupt structure (see table 7). there are 2 sfrs associated with the interrupts on the 89C536/538. they are the ie and ip. (see figures 6 and 7.) the function of the iph sfr is simple and when combined with the ip sfr determines the priority of each interrupt. the priority of each interrupt is determined as shown in the following table: priority bits interrupt priority level ip.x interrupt priority level 0 level 0 (lowest priority) 1 level 1 (highest priority) an interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. if an interrupt of equal or higher level priority is being serviced, the new interrupt will wait until it is finished before being serviced. if a lower priority level interrupt is being serviced, it will be stopped and the new interrupt serviced. when the new interrupt is finished, the lower priority level interrupt that was stopped will be completed. table 7. interrupt table source polling priority request bits hardware clear? vector address x0 1 ie0 n (l) 1 y (t) 2 03h t0 2 tp0 y 0bh x1 3 ie1 n (l) y (t) 13h t1 4 tf1 y 1bh sp 5 r1, ti n 23h t2 6 tf2, exf2 n 2bh notes: 1. l = level activated 2. t = transition activated ex0 ie (0a8h) enable bit = 1 enables the interrupt. enable bit = 0 disables it. bit symbol function ie.7 ea global disable bit. if ea = 0, all interrupts are disabled. if ea = 1, each interrupt can be individually enabled or disabled by setting or clearing its enable bit. ie.6 e not implemented. ie.5 et2 timer 2 interrupt enable bit. ie.4 es serial port interrupt enable bit. ie.3 et1 timer 1 interrupt enable bit. ie.2 ex1 external interrupt 1 enable bit. ie.1 et0 timer 0 interrupt enable bit. ie.0 ex0 external interrupt 0 enable bit. su00571 et0 ex1 et1 es et2 e ea 0 1 2 3 4 5 6 7 figure 6. ie registers px0 ip (0b8h) priority bit = 1 assigns higher priority priority bit = 0 assigns lower priority bit symbol function ip.7 e not implemented, reserved for future use. ip.6 e not implemented, reserved for future use. ip.5 pt2 timer 2 interrupt priority bit. ip.4 ps serial port interrupt priority bit. ip.3 pt1 timer 1 interrupt priority bit. ip.2 px1 external interrupt 1 priority bit. ip.1 pt0 timer 0 interrupt priority bit. ip.0 px0 external interrupt 0 priority bit. su00572 pt0 px1 pt1 ps pt2 e e 0 1 2 3 4 5 6 7 figure 7. ip registers
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 14 expanded data ram addressing the 89C536/538 has internal data memory that is mapped into four separate segments: the lower 128 bytes of ram, upper 128 bytes of ram, 128 bytes special function register (sfr), and 256 bytes expanded ram (eram). the four segments are: 1. the lower 128 bytes of ram (addresses 00h to 7fh) are directly and indirectly addressable. 2. the upper 128 bytes of ram (addresses 80h to ffh) are indirectly addressable only. 3. the special function registers, sfrs, (addresses 80h to ffh) are directly addressable only. 4. the 256-bytes expanded ram (eram, 00h ffh) are indirectly accessed by move external instruction, movx. the lower 128 bytes can be accessed by either direct or indirect addressing. the upper 128 bytes can be accessed by indirect addressing only. the upper 128 bytes occupy the same address space as the sfrs. that means they have the same address, but are physically separate from sfr space. when an instruction accesses an internal location above address 7fh, the cpu knows whether the access is to the upper 128 bytes of data ram or to sfr space by the addressing mode used in the instruction. instructions that use direct addressing access sfr space. for example: mov 0a0h,#data accesses the sfr at location 0a0h (which is p2). instructions that use indirect addressing access the upper 128 bytes of data ram. for example: mov @r0,#data where r0 contains 0a0h, accesses the data byte at address 0a0h, rather than p2 (whose address is 0a0h). the eram can be accessed by indirect addressing and movx instructions. this part of memory is physically located on-chip, logically occupies the first 256-bytes of external data memory. the eram is indirectly addressed, using the movx instruction in combination with any of the registers r0, r1 of the selected bank or dptr. an access to eram will not affect ports p0, p3.6 (wr#) and p3.7 (rd#). p2 sfr is output during external addressing. for example, movx @r0,#data where r0 contains 0a0h, accesses the eram at address 0a0h rather than external memory. an access to external data memory locations higher than ffh (i.e., 0100h to ffffh) will be performed with the movx dptr instructions in the same way as in the standard 80c51, so with p0 and p2 as data/address bus, and p3.6 and p3.7 as write and read timing signals. refer to figure 8. external data memory cannot be accessed using the movx with r0 or r1. this will always access the eram. the stack pointer (sp) may be located anywhere in the 256 bytes ram (lower and upper ram) internal data memory. the stack may not be located in the eram. eram 256 bytes upper 128 bytes internal ram lower 128 bytes internal ram special function register ff 00 ff 00 ff 00 80 80 external data memory ffff 0000 0100 su00868 figure 8. internal and external data memory address space
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 15 absolute maximum ratings 1, 2, 3 parameter rating unit operating temperature under bias 0 to +70 c storage temperature range 65 to +150 c voltage on ea /v pp pin to v ss 0 to +13.0 v voltage on any other pin to v ss 0.5 to +6.5 v maximum i ol per i/o pin 15 ma power dissipation (based on package heat transfer limitations, not device power consumption) 1 w notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the ac and dc electrical characteri stics section of this specification is not implied. 2. this product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted.
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 16 dc electrical characteristics t amb = 0 c to +70 c; 5v 10%; v ss = 0v symbol parameter test limits unit symbol parameter conditions min max unit v il input low voltage 4.5v < v cc < 5.5v 0.5 0.2v cc 0.1 v v ih input high voltage (ports 0, 1, 2, 3, ea ) 0.2v cc +0.9 v cc +0.5 v v ih1 input high voltage, xtal1, rst 0.7v cc v cc +0.5 v v ol output low voltage, ports 1, 2, 3 6 v cc = 4.5v i ol = 1.6ma 1 0.4 v v ol1 output low voltage, port 0, ale, psen 5, 6 v cc = 4.5v i ol = 3.2ma 1 0.4 v v oh output high voltage, ports 1, 2, 3 2 v cc = 4.5v i oh = 30 m a v cc 0.7 v v oh1 output high voltage (port 0 in external bus mode), ale 7 , psen 2 v cc = 4.5v i oh = 800 m a v cc 0.7 v i il logical 0 input current, ports 1, 2, 3 v in = 0.4v 1 50 m a i tl logical 1-to-0 transition current, ports 1, 2, 3 v in = 2.0v see note 3 650 m a i li input leakage current, port 0 0.45 < v in < v cc 0.3 10 m a i cc power supply current (see figure 16): see note 4 active mode v cc = 5.5v 60 ma idle mode freq = 24 mhz 25 ma power-down mode or clock stopped (see figure 20 for conditions) t amb = 0 c to 70 c 100 m a r rst internal reset pull-down resistor 40 225 k w notes: 1. capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus oper ations. in the worst cases (capacitive loading > 100pf), the noise pulse on the ale pin may exceed 0.8v. in such cases, it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. i ol can exceed these conditions provided that no single output sinks more than 5ma and no more than two outputs exceed the test conditions. 2. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the v cc 0.7 specification when the address bits are stabilizing. 3. pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. the transition curren t reaches its maximum value when v in is approximately 2v. 4. see figures 17 through 20 for i cc test conditions and figure 15 for limits.. 5. load capacitance for port 0, ale, and psen = 100pf, load capacitance for all other outputs = 80pf. 6. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 15ma maximum i ol per 8-bit port: 26ma maximum total i ol for all outputs: 71ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 7. ale is tested to v oh1 , except when ale is off then v oh is the voltage specification. 8. pin capacitance is characterized but not tested. pin capacitance is less than 25pf. pin capacitance of ceramic package is le ss than 15pf (except ea is 25pf).
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 17 ac electrical characteristics t amb = 0 c to +70 c, v cc = 5v 10%, v ss = 0v 1, 2, 3 variable clock 33mhz clock symbol figure parameter min max min max unit 1/t clcl 9 oscillator frequency speed versions : n (33mhz) 3.5 33 3.5 33 mhz t lhll 9 ale pulse width 2t clcl 40 21 ns t avll 9 address valid to ale low t clcl 25 5 ns t llax 9 address hold after ale low t clcl 25 5 ns t lliv 9 ale low to valid instruction in 4t clcl 65 55 ns t llpl 9 ale low to psen low t clcl 25 5 ns t plph 9 psen pulse width 3t clcl 45 45 ns t pliv 9 psen low to valid instruction in 3t clcl 60 30 ns t pxix 9 input instruction hold after psen 0 0 ns t pxiz 9 input instruction float after psen t clcl 25 5 ns t aviv 9 address to valid instruction in 5t clcl 80 70 ns t plaz 9 psen low to address float 10 10 ns data memory t rlrh 10, 11 rd pulse width 6t clcl 100 82 ns t wlwh 10, 11 wr pulse width 6t clcl 100 82 ns t rldv 10, 11 rd low to valid data in 5t clcl 90 60 ns t rhdx 10, 11 data hold after rd 0 0 ns t rhdz 10, 11 data float after rd 2t clcl 28 32 ns t lldv 10, 11 ale low to valid data in 8t clcl 150 90 ns t avdv 10, 11 address to valid data in 9t clcl 165 105 ns t llwl 10, 11 ale low to rd or wr low 3t clcl 50 3t clcl +50 40 140 ns t avwl 10, 11 address valid to wr low or rd low 4t clcl 75 45 ns t qvwx 10, 11 data valid to wr transition t clcl 30 0 ns t whqx 10, 11 data hold after wr t clcl 25 5 ns t qvwh 11 data valid to wr high 7t clcl 130 80 ns t rlaz 10, 11 rd low to address float 0 0 ns t whlh 10, 11 rd or wr high to ale high t clcl 25 t clcl +25 5 55 ns external clock t chcx 13 high time 17 t clcl t clcx ns t clcx 13 low time 17 t clcl t chcx ns t clch 13 rise time 5 ns t chcl 13 fall time 5 ns shift register t xlxl 12 serial port clock cycle time 12t clcl 360 ns t qvxh 12 output data setup to clock rising edge 10t clcl 133 167 ns t xhqx 12 output data hold after clock rising edge 2t clcl 80 50 ns t xhdx 12 input data hold after clock rising edge 0 0 ns t xhdv 12 clock rising edge to input data valid 10t clcl 133 167 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 100pf, load capacitance for all other outputs = 80pf. 3. interfacing the microcontroller to devices with float times up to 45ns is permitted. this limited bus contention will not cau se damage to port 0 drivers.
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 18 explanation of the ac symbols each timing symbol has five characters. the first character is always `t' (= time). the other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. the designations are: a address c clock d input data h logic level high i instruction (program memory contents) l logic level low, or ale p psen q output data r rd signal t time v valid w wr signal x no longer a valid logic level z float examples: t avll = time for address valid to ale low. t llpl = time for ale low to psen low. t pxiz ale psen port 0 port 2 a0a15 a8a15 a0a7 a0a7 t avll t pxix t llax instr in t lhll t plph t lliv t plaz t llpl t aviv su00006 t pliv figure 9. external program memory read cycle ale psen port 0 port 2 rd a0a7 from ri or dpl data in a0a7 from pcl instr in p2.0p2.7 or a8a15 from dpf a0a15 from pch t whlh t lldv t llwl t rlrh t llax t rlaz t avll t rhdx t rhdz t avwl t avdv t rldv su00025 figure 10. external data memory read cycle
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 19 t llax ale psen port 0 port 2 wr a0a7 from ri or dpl data out a0a7 from pcl instr in p2.0p2.7 or a8a15 from dpf a0a15 from pch t whlh t llwl t wlwh t avll t avwl t qvwx t whqx t qvwh su00026 figure 11. external data memory write cycle 012345678 instruction ale clock output data write to sbuf input data clear ri valid valid valid valid valid valid valid valid set ti set ri t xlxl t qvxh t xhqx t xhdx t xhdv su00027 123 0 4567 figure 12. shift register mode timing v cc 0.5 0.45v 0.7v cc 0.2v cc 0.1 t chcl t clcl t clch t clcx t chcx su00009 figure 13. external clock drive
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 20 v cc 0.5 0.45v 0.2v cc +0.9 0.2v cc 0.1 note: ac inputs during testing are driven at v cc 0.5 for a logic `1' and 0.45v for a logic `0'. timing measurements are made at v ih min for a logic `1' and v il max for a logic `0'. su00717 figure 14. ac testing input/output v load v load +0.1v v load 0.1v v oh 0.1v v ol +0.1v note: timing reference points for timing purposes, a port is no longer floating when a 100mv change from load voltage occurs, and begins to float when a 100mv change from the loaded v oh /v ol level occurs. i oh /i ol 20ma. su00718 figure 15. float waveform su00886 typ active mode max idle mode typ idle mode max active mode 30.00 20.00 10.00 481216 freq at xtal1 (mhz) 20 24 28 32 36 0.00 40.00 50.00 60.00 70.00 80.00 90.00 0 i cc (ma) figure 16. i cc vs. freq valid only within frequency specifications of the device under test
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 21 v cc p0 ea rst xtal1 xtal2 v ss v cc v cc v cc i cc (nc) clock signal su00719 figure 17. i cc test condition, active mode all other pins are disconnected v cc p0 ea rst xtal1 xtal2 v ss v cc v cc i cc (nc) clock signal su00720 figure 18. i cc test condition, idle mode all other pins are disconnected v cc 0.5 0.45v 0.7v cc 0.2v cc 0.1 t chcl t clcl t clch t clcx t chcx su00009 figure 19. clock signal waveform for i cc tests in active and idle modes t clch = t chcl = 5ns v cc p0 ea rst xtal1 xtal2 v ss v cc v cc i cc (nc) su00016 figure 20. i cc test condition, power down mode all other pins are disconnected. v cc = 2v to 5.5v
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 22 flash eprom program memory features ? 16k (89C536) or 64k (89c538) or electrically erasable internal program. ? up to 64 kilobyte external program memory if the internal program memory is switched off (ea = 0). ? programming and erasing voltage 12v 5% ? command register architecture byte programming (10 m s typical) auto chip erase 5 seconds typical (including preprogramming time) ? auto erase and auto program data polling toggle bit ? 100 minimum erase/program cycles ? advanced cmos flash eprom memory technology general description the 89C536/538 flash eprom memory augments eprom functionality with incircuit electrical erasure and programming. the 89C536/538 uses a command register to manage this functionality. the flash eprom reliably stores memory contents even after 100 erase and program cycles. the cell is designed to optimize the erase and programming mechanisms. in addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. the 89C536/538 uses a 12.0v 5%v pp supply to perform the auto program/erase algorithms. automatic programming the 89C536/538 is byte programmable using the automatic programming algorithm. the automatic programming algorithm does not require the system to time out or verify the data programmed. the typical room temperature chip programming time of the 89C536/538 is less than 5 seconds. automatic chip erase the device may be erased using the automatic erase algorithm. the automatic erase algorithm automatically programs the entire array prior to electrical erase. the timing and verification of electrical erase are controlled internal to the device. automatic programming algorithm the 89C536/538 automatic programming algorithm requires the user to only write a program setup command and a program command (program data and address). the device automatically times the programming pulse width, provides the program verify, and counts the number of sequences. a status bit similar to data polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming operation. automatic erase algorithm the 89C536/538 automatic erase algorithm requires the user to only write an erase setup command and erase command. the device will automatically preprogram and verify the entire array. then the device automatically times the erase pulse width, provides the erase verify, and counts the number of sequences. a status bit similar to data polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the erase operation. commands are written to the command register. register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry. during write cycles, the command register internally latches address and data needed for the programming and erase operations. for system design simplification, the 89C536/538 is designed to support either we or ce controlled writes. during a system write cycle, addresses are latched on the falling edge of we or ce , whichever occurs last. data is latched on the rising edge of we or ce , whichever occurs first. to simplify the following discussion, the we pin is used as the write cycle control pin through the rest of this text. all setup and hold times are with respect to the we signal. su00876 p1 rst p3.3 xtal2 xtal1 vss vdd p0 ea ale/we psen p2.7 p3.5 p2.0p2.5 p3.4 p2.6, p3.7, p3.1, p3.0 89C536/538 a0a7 1 ce 46 mhz pgm command/data v pp low pulse 0 oe a15 a8a13 a14 0000b +5v figure 21. erase/programming/verification
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 23 table 8. pin description pin name symbol function p1.0p1.7 p2.0p2.5, p3.4, p3.5 a0a7 a8a13, a14a15 input low order address bits input high order address bits p0.0p0.7 q0q7 data input/output p3.3 ce chip enable input p2.7 oe output enable input ale/we we write enable pin ea v pp program supply voltage p2.6, p3.7, p3.1, p3.0 ftest3ftest0 flash test mode selection v cc v cc power supply voltage (+5v) gnd gnd ground pin table 9. command definitions first bus cycle second bus cycle command bus cycles operation address data operation address data setup auto erase/auto erase (chip) 2 write x 30h write x 30h setup auto program/program 2 write x 40h write pa pd reset 2 write x ffh write x ffh notes: pa = address of memory location to be programmed pd = data to be programmed at location command definitions when low voltage is applied to the v pp pin, the contents of the command register default to 00h. placing high voltage on the v pp pin enables read/write operations. device operations are selected by writing specific data patterns into the command register. table 9 defines these 89C536/538 register commands. table 10 defines the bus operations of 89C536/538. table 10. operation v pp (1) ce oe we d00d07 read/write read(2) v pph v il v il vi h data out(3) standby(4) v pph v ih x x tristate write v pph v il v ih v il data in(5) notes: 1. v pph is the programming voltage specified for the device. 2. read operation with vpp = v pph may access array data (if write command is preceded) or silicon id codes. 3. with v pp at high voltage, the standby current equals i cc +i pp (standby). 4. refer to table 38 for valid datain during a write operation. 5. x can be v il or v ih .
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 24 set-up automatic chip erase/erase commands the automatic chip erase does not require the device to be entirely preprogrammed prior to executing the automatic setup erase command and automatic chip erase command. upon executing the automatic chip erase command, the device automatically will program and verify the entire memory for an allzero data pattern. when the device is automatically verified to contain an allzero pattern, a selftimed chip erase and verify begins. the erase and verify operations are complete when the data on dq7 iso1o at which time the device returns to the standby mode. the system is not required to provide any control or timing during these operations. when using the automatic chip erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verify command is required). the margin voltages are internally generated in the same manner as when the standard erase verify command is used. the automatic setup erase command is a command only operation that stages the device for automatic electrical erasure of all bytes in the array. automatic setup erase is performed by writing 30h to the command register. to command automatic chip erase, the command 30h must be written again to the command register. the automatic chip erase begins on the rising edge of the we and terminates when the data on dq7 is o1 a and the data on dq6 stops toggling for two consecutive read cycles, at which time the device returns to the standby mode. setup automatic program/program commands the automatic setup program is a commandonly operation that stages the devices for automatic programming. automatic setup program is performed by writing 40h to the command register. once the automatic setup program operation is performed, the next we pulse causes a transition to an active programming operation. addresses are internally latched on the falling edge of the we pulse. data is internally latched on the rising edge of the we pulse. the rising edge of we also begins the programming operation. the system is not required to provide further controls or timings. the device will automatically provide an adequate internally generated program pulse and verify margin. the automatic programming operation is completed when the data read on dq6 stops toggling for two consecutive read cycles and the data on dq7 and dq6 are equivalent to data written to these two bits at which time the device returns to the read mode (no program verify command is required; but data can be read out if oe is active low). reset command a reset command is provided as a means to safely abort the erase or programcommand sequences. following either setup command (erase or program) with two consecutive writes of ffh will safely abort the operation. memory contents will not be altered. should programfail or erasefail happen, two consecutive writes of ffh will reset the device to abort the operation. a valid command must then be written to place the device in the desired state. write operation status toggle bitdq6 the 89C536/538 features a atoggle bito as a method to indicate to the host system that the auto program/erase algorithms are either in progress or completed. while the automatic program or erase algorithm is in progress, successive attempts to read data from the device will result in dq6 toggling between one and zero. once the automatic program or erase algorithm is completed, dq6 will stop toggling and valid data will be read. the toggle bit is valid after the rising edge of the second we pulse of the two write pulse sequences. data pollingd07 the 89C536/538 also features data polling as a method to indicate to the host system that the automatic program or erase algorithms are either in progress or completed. while the automatic programming algorithm is in operation an attempt to read the device will produce the complement data of the data last written to dq7. upon completion of the automatic program algorithm an attempt to read the device will produce the true data last written to dq7. the data polling feature is valid after the rising edge of the second we pulse of the two write pulse sequences. while the automatic erase algorithm is in operation, dq7 will read a0o until the erase operation is completed. upon completion of the erase operation, the data on dq7 will read a1o. the data polling feature is valid after the rising edge of the second we pulse of two writes pulse sequences. the data polling feature is active during automatic program/erase algorithms. write operation the data to be programmed into flash should be inverted when programming. in other words to program the value `00', `ff' should be applied to port p0. system considerations during the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of chip enable. the magnitude of these transient current peaks is dependent on the output capacitance loading of the device. at a minimum, a 0.1 m f ceramic capacitor (high frequency, low inherent inductance) should be used on each device between v cc and gnd, and between v pp and gnd to minimize transient effects. symbol parameter min typ max unit condition c in v pph 14 pf vi n = 0v c out v pph 16 pf v out = 0v
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 25 command programming/data programming/erase operation dc characteristics t amb = 0 c to 70 c, v cc = 5v 10%, v pp = 12.0v 5% symbol parameter condition min typ max unit i li input leakage current v in = gnd to v cc 10 m a i lo output leakage current v out = gnd to v cc 10 m a i sb1 standby v cc current ce = vi h 1 ma i sb2 ce = v cc 0.3 v 1 100 m a i cc1 (read) operating v cc current i out = 0 ma, f=1 mhz 30 ma i cc2 i out = 0 ma, f=11mhz 50 ma i cc3 (program) in programming 50 ma i cc4 (erase) in erase 50 ma i cc5 (program verify) in program verify 50 ma i cc6 (erase verify) in erase verify 50 ma i pp1 (read) v pp current v pp =12.6 v 100 m a i pp2 (program) in programming 50 ma i pp3 (erase) in erase 50 ma i pp4 (program verify) in program verify 50 ma i pp5 (erase verify) in erase verify 50 ma v il input voltage 0.5 (note 5) 0.2v pp 0.3 v v ih 2.4 v cc +0.3v v (note 6) v ol output voltage low i ol =2.1ma 0.45 v v oh output voltage high i oh =400ua 2.4 v notes: 1. v cc must be applied before v pp and removed after v pp . 2. v pp must not exceed 14v including overshoot. 3. an influence may be had upon device reliability if the device is installed or removed while v pp =12v. 4. do not alter v pp from v il to 12v or 12v to v il when ce =v il 5. v il min. = 0.5v for pulse width 20ns. 6. if v ih is over the specified maximum value, programming operation cannot be guaranteed. 7. all currents are in rms unless otherwise noted. (sampled, not 100% tested.).
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 26 ac characteristics t amb = 0 c to 70 c, v cc = 5v 10%, v pp = 12v 5% symbol parameter condition min max unit t vps v pp setup time 100 ns t oes oe setup time 100 ns t cwc command programming cycles 150 ns t cep we programming pulse width 60 ns t eph1 we programming pulse width high 20 ns t ceph2 we programming pulse width high 100 ns t as address setup time 0 ns t ah1 address hold time for data polling 0 ns t ds data setup time 50 ns t dh data hold time 10 ns t cesp ce setup time before data polling/toggle bit 100 ns t ces ce setup time 0 ns t cesc ce setup time before command write 100 ns t vph v pp hold time 100 ns t df output disable time (note 2) 35 ns t dpa data polling/toggle bit access time 150 ns t aetc total erase time in auto chip erase 5(typ) s t avt total programming time in auto verify 15 300 s notes: 1. ce and oe must be fixed high during v pp transition from 5v to 12v or from 12v to 5v. 2. t df is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 27 timing waveform automatic programming one byte of data is programmed. verifying in fast algorithm and additional programming by external control are not required because these operations are executed automatically by an internal control circuit. programming completion can be verified by data polling and toggle bit checking after automatic verify starts. device outputs data during programming and data after programming on q7. q0 to q5(q6 is for toggle bit; see toggle bit, data polling, timing waveform) are in high impedance. su00877 v cc 5v 12v v pp a0a15 we ce oe q7 q0q5 setup auto program/ program command auto program & data polling t vph t ah1 address t vps t qes command in data in data in command in data data data data polling t df t dpa t dh t ds t dh t ds t cep t ceph1 t cep t cesp t ces t cesc t avt t cwc t as ov valid commad #40h figure 22. automatic programming timing waveform
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 28 a utomatic c hip e rase all data in the flash memory is erased. external erase verification is not required. erasure completion can be verified by data polling and toggle bit checking after automatic erase starts. device outputs 0 during erasure and 1 after erasure on q7, q0 to q5 (q6 is for toggle bit; see toggle bit, data polling, timing waveform) are in high impedance. su00878 v cc 5v 12v v pp a0a15 we ce oe q7 q0q5 ov setup auto chip erase/ erase command auto chip erase & data polling command in command in t vph t df t cesc t dpa t cesp t ces t cep t ceph 1 t cep t qes t cwc t vps data polling command in command in t ds t dh t ds t dh t aetc figure 23. automatic chip erase timing waveform reset su00879 12v 0v v pp a0a15 we ce oe ffh q0q7 command in t ds t cep t cwc v cc 5v ffh command in t vps t qes t ceph1 t cep t dh t ds t dh figure 24. reset timing waveform
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 29 toggle bit, data polling toggle bit appears in q6, when program/erase is operating. data polling appears in q7 during programming or erase. su00880 we 12v ce oe oe during p/e o7 during p o7 during p o0o5 data data data data data data data polling program/erase complete toggle bit high highz v pp highz highz highz data polling figure 25. toggle bit, data polling timing waveform
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 30 plcc44: plastic leaded chip carrier; 44 leads sot187-2
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 31 qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2
philips semiconductors preliminary specification 89C536/89c538 80c51 8-bit microcontroller family 16k/64k/512 flash 1998 apr 24 32 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1998 all rights reserved. printed in u.s.a. date of release: 05-98 document order number: 9397 750 03876
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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